VLSI efficient binary-to-residue converter for DSP applications
نویسندگان
چکیده
An area efficient binary-to-residue converter suitable for pipeline applications is proposed in this paper. This architecture uses multiple access on a ROM to generate the residues of a given number. It has been found that more than 25% reduction in the ROM area and a saving of one adder delay can be achieved at the expense of an extra ROM access to generate the residues of a 32 bit binary number.
منابع مشابه
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تاریخ انتشار 2000